New RISC-V hardware designs from 5G startup EdgeQ
Today, 5G cellular startup EdgeQ is announcing the addition of two new members to its advisory board—former Qualcomm CEO Paul Jacobs, and former Qualcomm CTO Matt Grob. Their mission is to cut the Total Cost of Ownership (TCO) of 5G cellular base stations in half by leveraging and extending open hardware RISC-V designs.
Traditionally, Radio Access Network (RAN) devices have tended to be closed design and deeply proprietary—much like consumer Wi-Fi and network hardware, they depend on closed-design ASICs with vendor-provided drivers and firmware. Such closed stacks generally cannot be upgraded to accommodate new protocols and use cases—for example, a Radio Unit or Distributed Unit designed for 4G networks must typically be replaced in its entirety in order to service 5G devices.
By contrast, vendors can implement their own OpenRAN solutions, which generally implement fewer functions in hardware, and more in software running on traditional operating systems such as Linux. But implementing such an O-RAN properly requires very deep protocol expertise to get right, and it tends to be extremely power-hungry and expensive to maintain once finished.
EdgeQ’s approach is to effectively split the difference between traditional, closed-silicon approaches and expensive O-RAN. EdgeQ licensed a reference RISC-V CPU design and added new hardware instructions to accelerate the computationally expensive vector math operations necessary to handle 4G and 5G communication and signal processing.
Adil Kidwai, EdgeQ’s VP and Head of Product Management, says the new instructions are not the standard RVV vector math extension. Kidwai describes EdgeQ’s ISA extension as a set of “custom vector instructions to achieve high performance at low power consumption for 5G infrastructure solutions.”
According to EdgeQ CEO Vinay Ravuri, the company’s innovative approach brings power consumption down from 100W (using a Xeon-based solution) to 10W, with nearly all the work done in EdgeQ’s SoC itself. In a cell tower’s DU, this can mean condensing separate hardware for machine-learning acceleration, timer sync, FEC acceleration, front and midhaul transport, and L1 processing all down into the single EdgeQ SoC—and, again according to EdgeQ, cut TCO by up to 50 percent.
Since the vector math instructions needed for 5G signal processing and communication are largely the same needed for machine-learning tasks, excess processing capacity in EdgeQ’s CPU can be allocated to local ML processing. According to Ravuri, cellular communication is a bursty workload, with the CPU spending most of its time idle. The RISC-V CPU’s cores can be directly partitioned, with some allocated to 4G/5G and some to ML, or workloads can be distributed on a Quality of Service (QoS) managed basis.
We think the most significant part of EdgeQ’s design is its flexibility. By providing customers true C/C++ access to its RISC-V SoC, EdgeQ is enabling not only innovations, but future adaptability. Such a system can be updated in-place to accommodate future protocol upgrades, where less flexible systems would need to be “forklift upgraded”—meaning you lift the old one up, slide in the new one, then cart the old one off to recycling.
EdgeQ is far from the only company in this general space—hard drive vendors Western Digital and Seagate have each begun implementing RISC-V designs in some upcoming hardware designs, and they’ve been doing it for similar reasons. We hope to see this expansion of RISC-V designs into formerly closed-silicon spaces continue—particularly in the consumer Wi-Fi world, where its greater programmability might mitigate the rise of e-waste as protocols change.
Listing image by EdgeQ